Dual-ended or Single-ended read

1. Dual ended when read/write ports are shared (6T cell)

2. Dual ended when you want to read fast; use a diff-sense-amp to sense a very small voltage difference.

Vias

rectangular vias better than square vias - why?

except in the case of - small interconnects (wires) (eg: M1) since rectangular vias have bigger side-wall caps. This would dominate the small wire capacitance.

Golden rule of thumb for small wires: close to driver - rectangular & close to load - square

Low Power Design Techniques

Sizing a n-input standard gate (where n≠1)

Load Capacitance = C_LOAD

Input Capacitance of the n-input NAND gate = C_N

Beta ratio of n-input NAND gate = β_N

Input Capacitance of equivalent inverter = C_INV

Beta ratio of equivalent Inverter = β_INV

(a) Logical Effort:

(b) Assume an inverter in place of the n-input NAND gate:

Now, the equivalent pull-down strength of the n-input NAND gate is:

Hence, adding WN_N and WP_N we get C_N:

E.g. for ND2, β_N = 1 and for INV β_INV = 2:

Wire resistive shielding

With a very long wire, the net RC for calculations is assumed to be 50% of the actual RC. This is because of resistive shielding of the long wire. The driver can only see 50% of the actual RC and increasing the drive-strength by more than that required for a 0.5RC won't give us any more benefit.

Sizing the bit-line pre-charge device

Margins

Slopes

Better Tracking

Sizing the bit-line keeper

The bit-line keeper should be sized so that the following criterion are met:

1. Writability

2. Keeper Leaker Ratio