Limiting cases for Number of SRAM Cells on ONE bit-line pair

1. Frequency (and hence, Power) -- Since with increased number of SRAM Cells, there will be more capacitance on the bit-lines. An increased capacitance entails an increased delay and also an increased power consumption - 0.5 x alpha x f x C x Vswing x VDD

2. Leakage -- While doing a read, only the cell that's being read is forcing a zero onto a bit-line (i.e. draining the capacitance on that bitline), but the pass transistors of other SRAM cells are OFF and if they leak such that the bit-line-bar is being pulled low -- then this can cause a problem since both the bit-line and the bit-line-bar shall be at zero voltages.