Negative Hold Time

Negative hold time is generally seen where a delay is already added in the data path inside the flop. This is usually done by the library vendor.Assume the flop which foundry gives us as a library part that has ports named as CLK-port, Data-Port. Now, in essence this is wrapper and should be treated as one. Inside this we have the actual flop whose ports are CLK-in, data-in. CLK-port is connected directly to CLK-in, Data-port goes through some delay element (either buffer or routing net) to Data-in. So even if the actual flop has hold requirement of say 0.2ns, if the data delay element value is 0.5ns, the library will give spec as -0.3ns HOLD requirement for the above flop. This signifies that even if the data changes 0.3ns before CLK, it can still be latched and as for the actual flop(inside the wrapper) it will still meet 0.2ns HOLD. (data changes after 0.2ns from clk change).Advantage:The biggest advantage is less iteration after layout...Easy and less painful synthesis (else HOLD fixing can be an iterative process)Disadvantage:We pay the cost in bigger setup times for above flops.

Limiting cases for Number of SRAM Cells on ONE bit-line pair

1. Frequency (and hence, Power) -- Since with increased number of SRAM Cells, there will be more capacitance on the bit-lines. An increased capacitance entails an increased delay and also an increased power consumption - 0.5 x alpha x f x C x Vswing x VDD

2. Leakage -- While doing a read, only the cell that's being read is forcing a zero onto a bit-line (i.e. draining the capacitance on that bitline), but the pass transistors of other SRAM cells are OFF and if they leak such that the bit-line-bar is being pulled low -- then this can cause a problem since both the bit-line and the bit-line-bar shall be at zero voltages.